An Efficient Low-Power Sigma-Delta modulator for Multi-Standard Wireless Applications

This paper describes the design and implementation of a recon ̄gurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital recon ̄gurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulations as well as transistor-level simulations of the modulator. HSPICE simulation results show that the proposed modulator achieves 76.8/78.9/80.8/85/ 89.5 dB peak signal-to-noise plus distortion ratio (SNDR) within the standards WiFi, WiMAX, WCDMA, Bluetooth and GSM with the bandwidth of 12.5MHz, 10MHz, 1.92MHz, 0.5MHz, and 250 kHz, respectively, under the power consumption of 37/37/12/5/5mW using a single 1V power supply.